The majority of present day integrated circuits (ICs) are implemented utilizing a plurality of interconnected field effect transistors (FETs), also referred to as metal oxide semiconductor field effect transistors (MOSFETs) or simply MOS transistors. A MOS transistor includes a gate electrode, which serves as a control electrode, and source and drain electrodes. A channel extends between the source and drain electrodes. Current flows through this channel upon application of a voltage (referred to as the “threshold voltage” or Vt) to the gate electrode sufficient to form an inversion region in the transistor substrate.
For MOS transistors employing metal gate stacks and high-k dielectrics, it is desirable that the target Vt (referred to herein as the “bandedge Vt”) corresponds to within 100 millivolts of the conduction band or valence band edge whether the device is NMOS or PMOS. It has, however, proven difficult to construct a metal gate MOS transistor having a bandedge Vt for several reasons. Fixed positive charges due to oxygen vacancies present in the high-k material may shift the transistor's threshold voltage away from the desired bandedge Vt. Furthermore, metals having work functions that yield bandedge threshold voltages (e.g., work functions of approximately 4.7-5.1 electron volts) are typically thermally unstable at temperatures exceeding 400 degrees Celsius. Such thermally unstable metals are generally unable to withstand the high temperatures experienced during source-drain activation annealing. For this reason, a gate-last approach is typically employed to construct MOS transistors including metal gates formed from thermally unstable metals. For example, a damascene process may be employed wherein a dummy gate is initially installed and subsequently removed via etching to produce a trench. A thermally unstable metal may then be deposited into the trench and polished to define a permanent metal gate.
While being generally well-suited for use in conjunction with long channel (LC) transistors (e.g., devices wherein the channel length exceeds a predetermined value, which may be, for example, approximately 0.1 μm), the above-described damascene process has certain disadvantages when utilized in conjunction with short channel (SC) transistors (e.g., devices wherein the channel length is equal to or less than the predetermined value). For example, due to the small size of the device, the entire dummy gate may not be removed during the etching process. Furthermore, when deposited over the open trench of an SC transistor, the metal gate material may pinch-off near the mouth of the trench before the trench is completely filled. Voiding can consequently occur within the body of the trench. Thus, for an IC including SC transistors and LC transistors, the damascene process is generally unacceptable and an etching process is generally utilized to construct the metal gates for both types of transistors thus generally preventing the use of thermally unstable metals in LC transistors to achieve bandedge voltage thresholds.
Accordingly, it would be desirable to provide a method for manufacturing a MOS transistor having short channel devices and long channel devices that permits bandedge voltage thresholds to be achieved for both the short and long channel devices. In particular, it would be desirable for such a method to permit thermally unstable metals to be utilized in the fabrication of the long channel devices, while also permitting oxygen vacancies present in the short channel devices to be repaired. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.